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| dram smj44400 austin semiconductor, inc. smj44400 rev. 2.0 10/01 austin semiconductor, inc. reserves the right to change products or specifications without notice. 1 features ? organized 1,048,576 x 4 options marking ? timing 80ns access -80 100ns access -10 120ns access -12 ? package(s) ceramic dip (400mils) jd no. 113 ceramic flatpack hr no. 308 ? operating temperature ranges military (-55 o c to +125 o c) m pin assignment (top view) available as military specifications ? smd 5962-90847 ? mil-std-883 20-pin dip (jd) 20-pin flatpack (hr) (400 mil) general description the smj44400 is a series of 4,194,304-bit dynamic ran- dom-access memories (drams), organized as 1,048,576 words of four bits each. this series employs state-of-the-art technology for high performance, reliability, and low-power operation. the smj44400 features maximum row access times of 80ns, 100ns, and 120ns. maximum power dissipation is as low as 360mw operating and 22mw standby. all inputs and outputs, including clocks, are compatible with series 54 ttl. all addressses and data-in lines are latched on-chip to simplify system design. data out is unlatched to allow greater system flexibility. 1m x 4 dram dynamic random-access memory for more products and information please visit our web site at www.austinsemiconductor.com ? single +5v 10% power supply ? enhanced page-mode operation for faster memory access p higher data bandwidth than conventional page-mode parts p random single-bit access within a row with a column address ? cas\-before-ras\ (cbr) refresh ? long refresh period: 1024-cycle refresh in 16ms (max) ? 3-state unlatched output ? low power dissipation ? all inputs/outputs and clocks are ttl compatible ? processing to mil-std-883, class b available 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 dq1 dq2 w\ ras\ a9 a0 a1 a2 a3 vcc vss dq4 dq3 cas\ oe\ a8 a7 a6 a5 a4 the smj44400 is offered in a 400-mil, 20-pin ceramic side-brazed dual-in-line package (jd suffix) and a 20-pin ceramic flatpack (hr suffix) that are characterized for operation from -55c to +125c. operation enhanced page mode enhanced page-mode operation allows faster memory access by keeping the same row address while selecting random column addresses. the time for row-address setup and hold and address multiplex is eliminated. the maximum number of columns that can be accessed is determined by the maximum ras\ low time and the cas\ page cycle time used. with minimum cas\ page cycle time, all 1024 columns specified by column addresses a0 through a9 can be accessed without intervening ras\ cycles. unlike conventional page-mode drams, the column- address buffers in this device are activated on the pin name function a0 - a9 address inputs cas\ column-address strobe dq1 - dq4 data inputs/outputs oe\ output enable ras\ row-address strobe w\ write enable vcc 5v supply vss ground
dram smj44400 austin semiconductor, inc. smj44400 rev. 2.0 10/01 austin semiconductor, inc. reserves the right to change products or specifications without notice. 2 (continued) enhanced paga mode (continued) falling edge of ras\. the buffers act as transparent or flow- through latches while cas\ is high. the falling edge of cas\ latches the column addresses. this feature allows the smj44400 to operate at a higher data bandwidth then conven- tional page-mode parts, since data retrieval begins as soon as column address is valid rather than when cas\ goes low. this performance improvement is referred to as enhanced page mode. valid column address can be presented immediately after row address hold time has been satisfied, usually well in advance of the maximum (access time from column address) has been satisfied. in the event that column addresses for the next cycle are valid at the time cas\ goes high, access time for the next cycle is determined by the later occurrence of t cac or t cpa (access time form rising edge of cas\). address (a0-a9) twenty address bits are required to decode 1 of 1,048,576 storage cell locations. ten row-address bits are set up on inputs a0 through a9 and latched onto the chip by ras\. the ten column-address bits are set up on pins a0 through a9 and latched onto the chip by cas\. all addresses must be stable on or before the falling edges of ras\ and cas\. ras\ is similar to a chip enable in that it activates the sense amplifiers as well as the row decoder. cas\ is used as a chip select, activating the output buffer as well as latching the address bits into the column-address buffer. write enable (w\) the read or write mode is selected through w\. a logic high on the w\ input selects the read mode and a logic low selects the write mode. the write-enable terminal can be driven from standard ttl circuits without a pullup resistor. the data input is disabled when the read mode is selected. when w\ goes low prior to cas\ (early write), data out reamins in the high-impedance state for the entire cycle permitting a write operation independent of the state of oe\. this permits early-write operation to be completed with oe\ grounded. data in/out (dq1 - dq4) the high-impedance output buffer provides direct ttl compatibility (no pullup resistor required) with a fanout of two series 54 ttl loads. data out is the same polarity as data in. the output is in the high-impedance (floating) state until cas\ and oe\ are brought low. in a read cycle the output becomes valid after all access times are satisfied. the output remains valid while cas\ and oe\ are low. cas\ or oe\ going high returns it to the high-impedance state. output enable (oe\) oe\ controls the impedance of the output buffers. when oe\ is high, the buffers remain in the high-impedance state. bringing oe\ low during a normal cycle activates the output buffers, putting them in the low-impedance state. it is necessary for both ras\ and cas\ to be brought low for the output buffers to go into the low-impedance state. once in the low-ompedance state, they remain in the low-impedance state until either oe\ or cas\ is brought high. refresh a refresh operation must be performed at least once every 16ms to retain data. this can be achieved by strobing each of the 1024 rows (a0-a9). a normal read or write cycle refreshes all bits in each row that is selected. a ras\-only operation can be used by holding cas\ at the high (inactive) level, conserving power as the output buffer remains in the high-impedance state. externally generated addresses must be used for a ras\-only refresh. hidden refresh can be performed while maintaining valid data at teh output pin. this is accomplished by holding cas\ at v il after a read operation and cycling ras\ after a specified precharge period, similar to a ras\-only refresh cycle. the external address is ignored during the hidden refresh cycles. cas\-before-ras\ (cbr) and hidden refresh cbr refresh is utilized by bringing cas\ low earlier than ras\ (see parameter t csr ) and holding it low after ras\ falls (see parameter t csr ). for successive cbr refresh cycles, cas\ can remain low while cycling ras\. the external address is ignored and the refresh address is generated internally. during cbr refresh cycles the outputs remain in the high-impedance state. hidden refresh can be performed while maintaining valid data at the output pins. thsi is accomplished by holding cas\ at vil after a read operation. ras\ is cycled after the specified read cycle parameters are met. hidden refresh can also be used in conjuction with an early-write cycle. cas\ is maintained at vil while ras\ is cycled, once all the specified early-write parameters are met. externally generated addresses must be used to specify the location to be accessed during the initial ras\ cycle of a hidden refresh operation. subsequent ras\ cycles (refresh cycles) use the internally- generated addresses and the external address is ignored. power up to achieve proper device operation, an initial pause of 200s followed by a minimum of eight initialization cycles is dram smj44400 austin semiconductor, inc. smj44400 rev. 2.0 10/01 austin semiconductor, inc. reserves the right to change products or specifications without notice. 3 (continued) power up (continued) required after full vcc level is achieved. these eight initial- ization cycles need to include at least one refresh (ras\-only or cbr) cycle. test mode an industry standard design for test (dft) mode is incorporated in the smj44400. a cbr with w\ low (wcbr) cycle is used to enter test mode. in the test mode, data is written into and read from eight sections of the array in parallel. all data is written into the array through dq1. data is comparted upon reading and if all bits are equal, all dq pins go high. if any one bit is different, all the dq pins go low. any combination read, write, read-write, or page-mode can be used in the test mode. the test mode function reduces test times by enabling the 1m x 4-bit dram to be tested as if it were a 512k dram where column address 0 is not used. a ras\-only or cbr refresh cycle is used to exit the dft mode. logic symbol 1 6 7 8 9 11 12 13 14 15 5 4 17 3 16 1 2 18 19 ram 1024k x 4 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 ras\ cas\ w\ oe\ dq1 dq2 dq3 dq4 & 23 , 21d g25 20d10/21d0 20d19/21d9 c20[row] g23/[refresh row] 24[power down] c21[column] g24 23c22 24,25en a 0 1 048 575 a, 22d 26 a, z26 1. this symbol is in accordance with ansi/ieee std. 91-1984 and iec publication 617-12. the pinouts illustrated are for the jd package. dram smj44400 austin semiconductor, inc. smj44400 rev. 2.0 10/01 austin semiconductor, inc. reserves the right to change products or specifications without notice. 4 functional block diagram ras\ cas\ w\ oe\ a0 a1 a9 timeing and control column address buffers row address buffers r o w d e c o d e r column decode sense amplifiers 128k array 128k array 128k array 128k array 128k array 128k array 8 2 10 10 16 16 i/o buffers 4 of 16 selection data in reg. data out reg. 16 16 2 4 4 absolute maximum ratings* voltage on vcc supply relative to vss...............-1v to +7.0v voltage range on any pin relative to vss.........-1v to +7.0v short circuit output current (per i/o).......................50ma power dissipation.................................................................1w storage temperature range..........................-65 c to +150 c operating temperature range......................-55c to +125c *stresses greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a stress rating only and functional opera- tion of the device at these or any other conditions above those indicated in the operation section of this specifica- tion is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. ** junction temperature depends upon package type, cycle time, loading, ambient temperature and airflow. recommended operating conditions sym description min nom max unit v cc supply voltage 4.5 5 5.5 v v ih high-level input voltage 2.4 6.5 v v il low-level input voltage 1 -1 0.8 v t a minimum operating temperature -55 c t c maximum operating case temperature 125 c 1. the algebraic convention, where the more negative (less positive) limit is designated as minimum, is used for logic-voltage levels only. dram smj44400 austin semiconductor, inc. smj44400 rev. 2.0 10/01 austin semiconductor, inc. reserves the right to change products or specifications without notice. 5 sym parameter test conditions min max min max min max unit v oh high-level output voltage i oh = -5ma 2.4 2.4 2.4 v v ol low-level output voltage i ol = 4.2ma 0.4 0.4 0.4 v i i input current (leakage) v cc = 5.5v, v i = 0v to 6.5v, all other pins = 0v to v cc 10 10 10 a i o output current (leakage) v cc = 5.5v, v o = 0v to v cc, cas\ high 10 10 10 a i cc1 read - or write-cycle current 1 v cc = 5.5v, minimum cycle 85 80 70 ma i cc2 standby current after 1 memory cycle, ras\ and cas\ high, v ih = 2.4v 444ma i cc3 average refresh current (ras\ only, or cbr\) 1 v cc = 5.5v, minimum cycle, ras\ cycling, cas\ high (ras\ only), ras\ low after cas\ low (cbr) 85 75 65 ma i cc4 average page current 2 v cc = 5.5v, t pc = minimum, ras\ low, cas\ cycling 50 40 35 ma -8 -10 -12 electrical characteristics and recommended operating conditions (-55 o c dram smj44400 austin semiconductor, inc. smj44400 rev. 2.0 10/01 austin semiconductor, inc. reserves the right to change products or specifications without notice. 7 timing requirements (continued) sym parameter min max min max min max unit t rad delay time, ras\ low to column address 1 15 40 20 50 20 65 ns t ral delay time, column addresss to ras\ high 40 50 55 ns t cal delay time, column addresss to cas\ high 40 50 55 ns t rcd delay time, ras\ low to cas\ low 1 20 60 25 75 25 90 ns t rpc delay time, ras\ high to cas\ low 0 0 0 ns t rsh delay time, cas\ low to ras\ high 20 25 30 ns t rwd delay time, ras\ low to w\ low (read-write operation only) 110 135 160 ns t clz cas\ to output in low z 2 000 ns t oed oe\ to data delay 20 25 30 ns t ref refresh time interval 16 16 16 ms t t tranistion time 3 -8 -10 -12 notes: 1. maximum value specified only to assure access time. 2. valid data is presented at the outputs after all access times are satisfied but can go from the high-impedance state to an i nvalid-data state prior to the specified access times as the outputs are driven when cas\ and oe\ are low. 3. transition times (rise and fall) for ras\ and cas\ are to be a minimum of 3ns and a maximum of 50ns. parameter measurement information figure 1. load circuit for timing parameters 1.31v output under test r l = 218 w cl = 100 pf 1 5v output under test r 1 = 828 w r 2 = 295 w cl = 100 pf 1 (b) alternate load circuit (a) load circuit notes: 1. c l includes probe and fixture capacitance. dram smj44400 austin semiconductor, inc. smj44400 rev. 2.0 10/01 austin semiconductor, inc. reserves the right to change products or specifications without notice. 8 read-cycle timing 1 notes: 1. valid data is presented at the outputs after all access times are satisfied but can go from the high-impedance state to an i nvalid-data state prior to the specified access tiems as the outputs are driven when cas\ and oe\ are low. dram smj44400 austin semiconductor, inc. smj44400 rev. 2.0 10/01 austin semiconductor, inc. reserves the right to change products or specifications without notice. 9 early-write-cycle timing dram smj44400 austin semiconductor, inc. smj44400 rev. 2.0 10/01 austin semiconductor, inc. reserves the right to change products or specifications without notice. 10 write-cycle timing dram smj44400 austin semiconductor, inc. smj44400 rev. 2.0 10/01 austin semiconductor, inc. reserves the right to change products or specifications without notice. 11 read-write cycle timing notes: 1. valid data is presented at the outputs after all access times are satisfied but can go from the high-impedance state to an i nvalid-data state prior to the specified access tiems as the outputs are driven when cas\ and oe\ are low. (1) dram smj44400 austin semiconductor, inc. smj44400 rev. 2.0 10/01 austin semiconductor, inc. reserves the right to change products or specifications without notice. 12 enhanced-page-mode read-cycle timing notes: 1. valid data is presented at the outputs after all access times are satisfied but can go from the high-impedance state to an i nvalid-data state prior to the specified access tiems as the outputs are driven when cas\ and oe\ are low. 2. access time is t cpa or t aa dependent. (1) (2) (2) dram smj44400 austin semiconductor, inc. smj44400 rev. 2.0 10/01 austin semiconductor, inc. reserves the right to change products or specifications without notice. 13 enhanced-page-mode write-cycle timing 2 notes: 1. referenced to cas\ or w\, whichever occurs last. 2. a read cycle or a read-write cycle can be intermixed with write cycles as long as read and read-write timing specifications are not violated. (1) (1) dram smj44400 austin semiconductor, inc. smj44400 rev. 2.0 10/01 austin semiconductor, inc. reserves the right to change products or specifications without notice. 14 enhanced-page-mode read-write-cycle timing 2 notes: 1. valid data is presented at the outputs after all access times are satisfied but can go from the high-impedance state to an i nvalid-data state prior to the specified access times as the outputs are driven when cas\ and oe\ are low. 2. a read or write cycle can be intermixed with read-write cycles as long as the read and write timing specifications are not v iolated. (1) (1) dram smj44400 austin semiconductor, inc. smj44400 rev. 2.0 10/01 austin semiconductor, inc. reserves the right to change products or specifications without notice. 15 ras\-only refresh timing dram smj44400 austin semiconductor, inc. smj44400 rev. 2.0 10/01 austin semiconductor, inc. reserves the right to change products or specifications without notice. 16 automatic-cbr-refresh-cycle timing dram smj44400 austin semiconductor, inc. smj44400 rev. 2.0 10/01 austin semiconductor, inc. reserves the right to change products or specifications without notice. 17 hidden-refresh-cycle (read) timing notes: 1. valid data is presented at the outputs after all access times are satisfied but can go from the high-impedance state to an i nvalid-data state prior to the specified access times as the outputs are driven when cas\ and oe\ are low. (1) dram smj44400 austin semiconductor, inc. smj44400 rev. 2.0 10/01 austin semiconductor, inc. reserves the right to change products or specifications without notice. 18 mechanical definitions* asi case #113 (package designator jd) smd 5962-90847, case outline u note: these dimensions are per the smd. asi's package dimensional limits may differ, but they will be within the smd limits. * all measurements are in inches. ea c a q l e b b2 s1 d e d1 pin 1 min max a --- 0.175 b 0.015 0.021 b2 0.045 0.065 c 0.008 0.014 d 0.980 1.030 d1 0.890 0.910 e 0.380 0.410 ea 0.385 0.420 e q 0.015 0.060 l 0.125 0.200 s1 --- 0.070 symbol smd specifications 0.100 bsc dram smj44400 austin semiconductor, inc. smj44400 rev. 2.0 10/01 austin semiconductor, inc. reserves the right to change products or specifications without notice. 19 mechanical definitions* asi case #308 (package designator hr) smd 5962-90847, case outline x note: these dimensions are per the smd. asi's package dimensional limits may differ, but they will be within the smd limits. * all measurements are in inches. d e l e b s 1234 1 23 4 1234 1234 1 23 4 1234 1234 1234 1234 1234 1234 1 23 4 1234 1234 1 23 4 1234 1234 1 23 4 1234 1234 1 23 4 1234 1234 1 23 4 1234 1234 1 23 4 1234 123 1 2 3 123 123 1 2 3 123 123 1 2 3 123 1 2 3 123 123 1 2 3 123 123 1 2 3 123 123 1 2 3 123 123 1 2 3 123 123 1 2 3 123 123 1 2 3 123 123456 123456 1234 1234 c a q min max a 0.080 0.100 b 0.015 0.021 c 0.004 0.010 d 0.690 0.710 e 0.483 0.497 e l 0.340 0.370 q 0.025 0.035 s 0.101 0.133 symbol smd specifications 0.050 typ dram smj44400 austin semiconductor, inc. smj44400 rev. 2.0 10/01 austin semiconductor, inc. reserves the right to change products or specifications without notice. 20 *available processes m = extended temperature range -55 o c to +125 o c ordering information example: smj44400-12jdm device number speed ns package type process smj44400 -80 jd /* smj44400 -10 jd /* smj44400 -12 jd /* example: smj44400-80hrm device number speed ns package type process smj44400 -80 hr /* smj44400 -10 hr /* smj44400 -12 hr /* dram smj44400 austin semiconductor, inc. smj44400 rev. 2.0 10/01 austin semiconductor, inc. reserves the right to change products or specifications without notice. 21 asi to dscc part number cross reference* asi package designator jd ti p ar t #** smd p ar t # smj44400-12/jdm 5962-9084701mua smj44400-10/jdm 5962-9084702mua smj44400-80/jdm 5962-9084703mua * asi part number is for reference only. orders received referencing the smd part number will be processed per the smd. ** parts are listed on smd under the old texas instruments part number. asi purchased this product line in november of 1999. asi package designator hr ti p ar t #** smd p ar t # smj44400-12/hrm 5962-9084701mxa smj44400-10/hrm 5962-9084702mxa smj44400-80/hrm 5962-9084703mxa |
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